0 to 16V, Hot-Swap Controller with 10-Bit
Current, Voltage Monitor, and 4 LED Drivers
14
Table 1b. Register Address Map (General)
Table 2. chxen Register Format
REGISTER
NAME
DESCRIPTION
ADDRESS
(HEX CODE)
RESET
VALUE
READ/
WRITE
mon_range
MON input range setting
0x18
0x00
R/W
cbuf_chx_store
Selective enabling of circular buffer
0x19
0x0F
R/W
ifast2slow
Current threshold fast-to-slow ratio setting
0x30
0x0F
R/W
status0
Slow-trip and fast-trip comparators status register
0x31
0x00
R
status1
PROT, MODE, and ON inputs status register
0x32
R
status2
Fast-trip threshold maximum range setting bits, from IRNG three-
state input
0x33
R/W
status3
LATCH, POL, ALERT, and PG status register
0x34
R
fault0
Status register for undervoltage detection (warning or critical)
0x35
0x00
R/C
fault1
Status register for overvoltage detection (warning or critical)
0x36
0x00
R/C
fault2
Status register for overcurrent detection (warning)
0x37
0x00
R/C
pgdly
Delay setting between MON measurement and PG assertion
0x38
0x00
R/W
fokey
Load register with 0xA5 to enable force-on function
0x39
0x00
R/W
foset
Register that enables force-on function
0x3A
0x00
R/W
chxen
Channel enable bits
0x3B
R/W
dgl_i
OC deglitch enable bits
0x3C
0x00
R/W
dgl_uv
UV deglitch enable bits
0x3D
0x00
R/W
dgl_ov
OV deglitch enable bits
0x3E
0x00
R/W
cbufrd_hibyonly
Circular buffers readout mode: 8 bit or 10 bit
0x3F
0x0F
R/W
cbuf_dly_stop
Circular buffer stop delay; number of samples recorded to the circu-
lar buffer after channel shutdown
0x40
0x19
R/W
peak_log_rst
Reset control bits for peak-detection registers
0x41
0x00
R/W
peak_log_hold
Hold control bits for peak-detection registers
0x42
0x00
R/W
LED_flash
LED flash/GPIO enable register
0x43
0x0F
R/W
LED_ph_pu
LED phase/weak pullup enable register
0x44
0x00
R/W
LED_state
LED pins voltage state register (LED pins set open)
0x45
R
Description:
Channel enable bits
Resister Title:
chxen
Register Address:
0x3B
RESET
VALUE
R
R
R
R
R/W
R/W
R/W
R/W
Unused
Unused
EN2
EN1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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